NVIDIA's GLM-5.3-Flash-FP4-Local: the QAD re-quant decoded, and why it can't swap into the 4× switchless NVFP4 lane

NVIDIA’s new FP4-Local checkpoint re-quantizes GLM-5.3-Flash with quantization-aware distillation and compressed expert scales, cutting it to 164.6 GiB with near-baseline accuracy — but it requires a forked vLLM stack (B12X kernels, modelopt_mixed loader), and the checkpoint’s own author says 4× Spark clusters gain little from it: the quant exists to buy back KV cache on 2-node setups, a constraint four nodes don’t have.

GLM-5.3-Flash quants compared: five NVFP4 checkpoints in depth, the top-20 of every precision on accuracy, and a W4A16-int4 vs NVFP4 head-to-head

RadixArk, NVIDIA, RedHatAI, LibertAI and local-inference-lab all ship an NVFP4 GLM-5.3-Flash that differs far less in size (195-204 GB) than in quantization scheme: W4A4 vs weight-only, what stays BF16, MTP handling, calibration, and one checkpoint whose expert weights are actually retrained — with the tensor-scale math to verify each card’s claims. A same-day appendix widens the lens to the 20 most-downloaded quants of any precision, accuracy only; a second-day appendix puts the two most heavily audited cards — canada-quant’s int4 W4A16 and NVIDIA’s NVFP4 — side by side on evidence quality and scheme mechanics, and explains why no honest head-to-head number exists yet.

Reclaiming the GB10 display carve-out: what 'more RAM on DGX Spark' actually buys a TP4 serving cluster

Two community techniques unlock the GB10’s idle 2 GiB display-reserved memory: a patched-driver kernel reclaim into Linux RAM (self-reported, no KV-pool benefit proven) and a DRM display-buffer route into CUDA (community-confirmed, +250k KV tokens but ~60-70% bandwidth). Neither helps glm-v53-flash-4x-noswitch today; verdict monitor-and-wait.

TensorFold vs vLLM for GLM-5.3-Flash FP8: what the new engine actually is, and whether its speedups can move a 4x DGX Spark ring

TensorFold’s headline GLM gains come from EXL3-trellis kernels and a lane scheduler that are quantization- and topology-specific — upstream CUDA is 10 days old, TP2-only, and one-request-at-a-time for GLM. For an FP8 checkpoint on TP4-over-switchless-ring with DFlash2 + SparkCache, the verdict is pass-and-watch; the one transferable idea is latent FP8 KV.